Non-Volatile Memory (NVM) is very attractive because it permits the storage of data for some length of time. The ability to store data has enabled the information age and prompt, reliable access to this data is one of the reasons why Solid State Drives (SSDs) have become so popular in recent years. Also, Solid-state drives (SSDs) that are built using NAND flash memory are becoming more and more common as their price decreases.
In order to reduce the cost of NAND flash, there is a desire to move to smaller and smaller process geometries. However, as shown in FIG. 1, moving to smaller process geometries reduces the reliability of the NAND flash memory. In the graph 10 of FIG. 1, the error rate of NAND flash memory increases (i.e., gets worse) when moving from one process node to the next. In FIG. 1, the x-axis represents the Program Erase (PE) cycles and the y-axis represents the average Raw Bit Error Rate (RBER) per page.
NAND flash memory, however, is not particularly reliable as a storage medium because NAND flash memory often suffers from errors. Because NVMs are never error free, and to ensure data is reliably protected, a NVM controller must implement a robust error correction method. Error correction methods are currently migrating from classical Error Correction Codes (ECCs) to Low-Density Parity Check (LDPC) codes. LDPC codes are a stronger class of ECC and as such are capable of correcting more errors for the same amount of parity overhead. LDPC codes are more complex to implement in VLSI circuits, however, because of Moore's Law, the additional cost of utilizing LDPC codes in VLSI circuits is decreasing as NVM controllers are implemented in newer and smaller geometries.
A read error occurs in a NAND flash memory when the read state differs from the write state. Such read errors can be corrected by modifying or offsetting a voltage associated with a threshold between two bit states. Improvements in the setting or modifying of NAND flash memory read voltage thresholds are desirable.